The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a composite semiconductor substrate having high-voltage elements isolated from each other.
In a conventional composite semiconductor device having a large-current power element with a high breakdown voltage and a control circuit element integrated into a monolithic structure, in order to improve the current efficiency, the power element, e.g., a power MOSFET is designed such that a source electrode and a gate electrode are formed on the same substrate surface as the control circuit element, and a drain electrode is formed on the opposite surface (lower surface) of the substrate. Therefore, this device requires a structure for electrically isolating the power element and the control circuit element from each other.
A p-n junction isolation technique is generally employed as a technique of isolating such elements. More specifically, a p-type epitaxial layer is formed on an n-type semiconductor substrate, and an n-type epitaxial layer is further formed on the resultant structure. A p-type impurity layer is then formed by diffusion to extend from the surface of the n-type epitaxial layer to the p-type epitaxial layer through the n-type epitaxial layer. As a result, the control circuit element region is surrounded by these p-type layers, and the resultant p-n junction is reverse-biased, thereby electrically isolating the power element and the control circuit element from each other.
As an insulation/isolation method using an SOI substrate, a technique shown in FIGS. 4A and 4B is disclosed in IEEE PESC (Power Electronics Specialist Conference), '88 RECORD No. 7 C-5 (April, 1988). In this technique, as shown in FIG. 4A, first and second silicon substrates 59 and 60 are bonded to each other through a silicon dioxide film 55, and an insulating isolation groove 61 is formed by depositing a silicon dioxide film 57 on the side walls of a V- groove formed in the first silicon substrate 59 and filling the groove with polycrystalline silicon 58. A control circuit element region 52 surrounded by the insulating isolation groove 61 and having a heavily doped layer 54 is formed on the first silicon substrate 59. A portion 53 adjacent to the region 52 on the first silicon substrate 59 is removed by etching. Subsequently, as shown in FIG. 4B, a silicon layer is epitaxially grown on the portion, of the substrate 59, from which the portion 53 is removed by etching, and a power MOSFET is formed in this epitaxial growth layer 56. A drain electrode (not shown) of this transistor is formed on the lower surface of the second silicon substrate 60.
When a power element having a current path, formed to extend from the upper surface to the lower surface of a silicon substrate, and a control circuit element are to be integrated into a monolithic structure, a high breakdown voltage is very difficult to obtain by element isolation based on a p-n junction. In addition, according to the conventional isolation technique using the above-described SOI substrate, although a high breakdown voltage can be obtained, a complicated manufacturing process is required, and an increase in cost cannot be avoided because a power element region is formed by epitaxial grown after the formation of a control circuit element.